74LV138PW Datasheet PDF - NXP

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74LV138PW
NXP

Part Number 74LV138PW
Description 3-to-8 line decoder/demultiplexer
Page 16 Pages


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74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 4 March 2016
Product data sheet
1. General description
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C



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NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LV138D
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
74LV138DB
40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
74LV138PW
40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74LV138BQ
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
4. Functional diagram



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Fig 3. Functional diagram
74LV138
Product data sheet
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All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 16



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NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y0 to Y7
VCC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 16



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NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
Output
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXL XXXHHHHHHHH
L L HL L L L HHHHHHH
L L HHL L HL HHHHHH
L L HL HL HHL HHHHH
L L HHHL HHHL HHHH
L L HL L HHHHHL HHH
L L HHL HHHHHHL HH
L L HL HHHHHHHHL H
L L HHHHHHHHHHHL
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
IOK output clamping current
IO output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
0.5
[1] -
[1] -
-
+7.0 V
20 mA
50 mA
25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
SO16 package
- 50 mA
50 - mA
65 +150 C
[2] -
500 mW
(T)SSOP16 package
[3] -
500 mW
DHVQFN16 package
[4] -
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 16



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