74HCT423 Datasheet PDF - NXP

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74HCT423
NXP

Part Number 74HCT423
Description Dual retriggerable monostable multivibrator
Page 24 Pages


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74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
Rev. 6 — 19 December 2011
Product data sheet
1. General description
74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC423; 74HCT423 dual retriggerable monostable multivibrator with reset has two
methods of output pulse width control.
1. The minimum pulse width is essentially determined by the selection of an external
resistor (REXT) and capacitor (CEXT), see Section 12.1.
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output
HIGH and also inhibits the triggering. Figure 10 and Figure 11 illustrate pulse control
by reset.
The nA and nB inputs’ Schmitt trigger action makes them highly tolerant to slower input
rise and fall times.
The 74HC423; 74HCT423 are identical to the 74HC123; 74HCT123 except that they
cannot be triggered via the reset input.
2. Features and benefits
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C



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NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74HC423N 40 C to +125 C DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT423N
74HC423D 40 C to +125 C
74HCT423D
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC423BQ 40 C to +125 C
74HCT423BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
74HCT423DB 40 C to +125 C SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT423PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
1A 1
1B 2
1RD 3
2A 9
2B 10
2RD 11
Fig 1. Functional Diagram
S
Q
T
Q
RD
S
Q
T
Q
RD
14
1CEXT
15
1REXT/ CEXT
13
1Q
4 1Q
6
2CEXT
7 2REXT/CEXT
5 2Q
12 2Q
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74HC_HCT423
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 19 December 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
1 1A
9 2A
2 1B
10 2B
3 1RD
11 2RD
Fig 2. Logic symbol
1CEXT 14
2CEXT 6
1REXT/CEXT 15
2REXT/CEXT 7
S
Q
T
Q
RD
1Q 13
2Q 5
1Q 4
2Q 12
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14
CX
15
RCX
1
&
2
3
R
13
4
6
CX
7
RCX
9
&
10
5
12
11 R
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Fig 3. IEC Logic symbol
REXT/CEXT
VCC
RD
R
CL
VCC
VCC
CL
CL
R
A
B
Fig 4. Logic diagram
74HC_HCT423
Product data sheet
CL CL
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 19 December 2011
Q
Q
001aah799
© NXP B.V. 2011. All rights reserved.
3 of 24



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NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74HC423
74HCT423
1A 1
1B 2
1RD 3
1Q 4
2Q 5
2CEXT 6
2REXT/CEXT 7
GND 8
74HC423
74HCT423
16 VCC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
9 2A
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terminal 1
index area
1B 2
1RD 3
1Q 4
2Q 5
2CEXT 6
2REXT/CEXT 7
VCC(1)
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
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Transparent top view
Fig 5. Pin configuration DIP16, SO16 and (T)SSOP16
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as
supply pin or input
Fig 6. Pin configuration DHVQFN16
5.2 Pin description
Table 2. Pin description
Symbol
1A, 2A
1B, 2B
1RD, 2RD
1Q, 2Q
GND
1Q, 2Q
1CEXT, 2CEXT
1REXT/CEXT, 2REXT/CEXT
VCC
Pin
1, 9
2, 10
3, 11
4, 12
8
13, 5
14, 6
15, 7
16
Description
trigger input (negative edge triggered)
trigger input (positive edge triggered)
direct reset (active LOW)
output (active LOW)
ground (0 V)
output (active HIGH)
external capacitor connection
external resistor/capacitor connection
supply voltage
74HC_HCT423
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 19 December 2011
© NXP B.V. 2011. All rights reserved.
4 of 24



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