74HCT4066 Datasheet PDF - NXP

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74HCT4066
NXP

Part Number 74HCT4066
Description Quad single-pole single-throw analog switch
Page 24 Pages


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74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
Rev. 8 — 3 December 2015
Product data sheet
1. General description
The 74HC4066; 74HCT4066 is a quad single pole, single throw analog switch. Each
switch features two input/output terminals (nY and nZ) and an active HIGH enable input
(nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Input levels nE inputs:
For 74HC4066: CMOS level
For 74HCT4066: TTL level
Low ON resistance:
50 (typical) at VCC = 4.5 V
45 (typical) at VCC = 6.0 V
35 (typical) at VCC = 9.0 V
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C



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NXP Semiconductors
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74HC4066D 40 C to +125 C
74HCT4066D
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HC4066DB 40 C to +125 C
74HCT4066DB
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HC4066PW 40 C to +125 C
74HCT4066PW
TSSOP14 plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
74HC4066BQ 40 C to +125 C
74HCT4066BQ
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
4. Functional diagram
 <
=
 (
 <
 (
=
 <
=
 (
 <
 (
=
DDG
Fig 1. Logic symbol




Q(

 





 




D
Fig 2. IEC logic symbol

  ;


  ;


  ;

 
  ;
 
E
DDG 
Q<
9&&
9&&
*1'
Q=
DDG 
Fig 3. Schematic diagram (one switch)
74HC_HCT4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 3 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 24



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5. Pinning information
5.1 Pinning
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
< 
= 
= 
< 
( 
( 
*1' 
 9&&
 (
 (

 <
 =
 =
 <
DDG 
Fig 4. Pin configuration for SO14 and (T)SSOP14
5.2 Pin description
Table 2. Pin description
Symbol
1Z, 2Z, 3Z, 4Z
1Y, 2Y, 3Y, 4Y
GND
1E, 2E, 3E, 4E
VCC
Pin
2, 3, 9, 10
1, 4, 8, 11
7
13, 5, 6, 12
14
6. Functional description
Table 3. Function table[1]
Input nE
L
H
[1] H = HIGH voltage level;
L = LOW voltage level.
WHUPLQDO
LQGH[DUHD
= 
= 
< 
( 
( 

9&& 
 (
 (
 <
 =
 =
DDF
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 5. Pin configuration for DHVQFN14
Description
independent input or output
independent input or output
ground (0 V)
enable input (active HIGH)
supply voltage
Switch
OFF
ON
74HC_HCT4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 3 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 24



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NXP Semiconductors
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
ISK
ISW
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VSW < 0.5 V or VSW > VCC + 0.5 V
VSW = 0.5 V to VCC + 0.5 V
Tamb = 40 C to +125 C
SO14, (T)SSOP14 and DHVQFN14
packages
0.5
-
-
[1] -
-
-
65
[2]
-
+11.0
20
20
25
50
50
+150
V
mA
mA
mA
mA
mA
C
500 mW
P power dissipation
per switch
- 100 mW
[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC
VI
VSW
Tamb
t/V
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise
and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
74HC4066
Min Typ Max
2.0 5.0 10.0
GND
-
VCC
GND
-
VCC
40 +25 +125
- - 625
- 1.67 139
- - 83
- - 35
74HCT4066
Min Typ Max
4.5 5.0 5.5
GND
-
VCC
GND
-
VCC
40 +25 +125
---
- 1.67 139
---
---
Unit
V
V
V
C
ns/V
ns/V
ns/V
ns/V
74HC_HCT4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 3 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 24



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