74HCT08D-Q100 Datasheet PDF - NXP


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74HCT08D-Q100
NXP

Part Number 74HCT08D-Q100
Description Quad 2-input AND gate
Page 14 Pages

74HCT08D-Q100 datasheet pdf
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74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
Rev. 1 — 16 July 2012
Product data sheet
1. General description
The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Complies with JEDEC standard JESD8-1A
Input levels:
For 74HC08-Q100: CMOS level
For 74HCT08-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC08D-Q100 40 C to +125 C SO14
74HCT08D-Q100
74HC08PW-Q100 40 C to +125 C TSSOP14
74HCT08PW-Q100
74HC08BQ-Q100 40 C to +125 C DHVQFN14
74HCT08BQ-Q100
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1



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NXP Semiconductors
4. Functional diagram
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
1
&
2
3
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna222
Fig 1. Logic symbol
4&
5
6
9&
10
8
12 & 11
13
mna223
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna221
Fig 3. Logic diagram (one gate)
+&4
+&74
$ 
% 
< 
$ 
% 
< 
*1' 
 9&&
 %
 $
 <
 %
 $
 <
DDD
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
+&4
+&74
WHUPLQDO 
LQGH[ DUHD
% 
< 
$ 
% 
< 
*1' 
 %
 $
 <
 %
 $
DDD
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 5. Pin configuration DHVQFN14
74HC_HCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
© NXP B.V. 2012. All rights reserved.
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NXP Semiconductors
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
nB
L
H
L
H
Output
nY
L
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
-
50
65
[2] -
+7
20
20
25
50
-
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
© NXP B.V. 2012. All rights reserved.
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NXP Semiconductors
74HC08-Q100; 74HCT08-Q100
Quad 2-input AND gate
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
9. Static characteristics
74HC08-Q100
Min Typ
2.0 5.0
0-
0-
40 -
--
- 1.67
--
Max
6.0
VCC
VCC
+125
625
139
83
74HCT08-Q100
Min Typ Max
4.5 5.0 5.5
0-
0-
40 -
VCC
VCC
+125
---
- 1.67 139
---
Unit
V
V
V
C
ns/V
ns/V
ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC08-!00
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 4.5 V
1.5 1.2 -
1.5
-
1.5
-V
3.15 2.4 - 3.15
-
3.15
-V
VCC = 6.0 V
4.2 3.2 -
4.2
-
4.2
-V
VIL LOW-level VCC = 2.0 V
input voltage VCC = 4.5 V
- 0.8 0.5
-
0.5
-
0.5 V
- 2.1 1.35 -
1.35
-
1.35 V
VCC = 6.0 V
- 2.8 1.8
-
1.8
-
1.8 V
VOH HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V 1.9 2.0
-
1.9
-
1.9
-V
IO = 20 A; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = 20 A; VCC = 6.0 V 5.9 6.0 -
5.9
-
5.9
-V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 -
3.84
-
3.7
-V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 -
5.34
-
5.2
-V
VOL LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 4.5 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 6.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 4.0 mA; VCC = 4.5 V
- 0.15 0.26
-
0.33
-
0.4 V
IO = 5.2 mA; VCC = 6.0 V
- 0.16 0.26
-
0.33
-
0.4 V
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
- - 0.1 -
1
-
1 A
ICC
supply current VI = VCC or GND; IO = 0 A;
-
- 2.0
-
20
-
40 A
VCC = 6.0 V
74HC_HCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 July 2012
© NXP B.V. 2012. All rights reserved.
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