74HC699 Datasheet PDF - STMicroelectronics

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74HC699
STMicroelectronics

Part Number 74HC699
Description 4 BIT BINARY COUNTER/REGISTER
Page 22 Pages


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M54/74HC696/697
M54/74HC698/699
HC696/698 U/D DECADE COUNTER/REGISTER (3-STATE)
HC697/699 U/D 4 BIT BINARY COUNTER/REGISTER (3-STATE)
. HIGH SPEED
fMAX = 50 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
. 15 LSTTL LOADS (for QA to QD)
10 LSTTL LOADS (for RCO)
SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 6 mA (MIN.) FOR QA TO QD
|IOH| = IOL = 4 mA (MIN.) FOR RCO OUTPUT
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH LSTTL 54/74LS696/697/698/699
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
DESCRIPTION
The HC696/697 are high speed CMOS up/down
counters fabricated with silicon gate C2MOS
technology. They achieve the high speed operation
similar to equivalent LSTTL while maintaining the
CMOS low power dissipation. The HC696/698 are
BCD DECADE COUNTER, and the HC697/699 are
4-BIT BINARY COUNTER. Both devices have
register.
They count on the positive edge of the counter clock
input (CCK) when selected by the ”Counter Mode”.
If the input U/D is held ”H”, the internal counter
counts up, and held ”L”, counts down. The internal
counter’s outputs are stored in the output register at
the positive edge of register clock (RCK).
The counter features enable P and enable T and a
ripple-carry output for easy expansion. the
register/counter select input, R/C, selects the
counter when low or the register when high for the
three state outputs, QA, QB, Qc and QD.
Both the counter clock CCK and register clock RCK
are positive-edge triggered. The counter clear
CCLR is active low and is synchronous for
HC698/699, and asynchronous for HC696/697.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
March 1993
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M54/M74HC696/697/698/699
PIN DESCRIPTION
PIN No
1
2
3, 4, 5, 6
7, 14
8
9
11
12
13
15, 16, 17,
18
19
10
20
SYMBOL
U/D
CCK
A to D
EMP/ENT
CCLR
RCK
R/C
G
LOAD
QA to QD
RCO
GND
VCC
NAME AND FUNCTION
Up Down Counter Selector
Counter Clock
Data Inputs
Enable P and T
Counter Clear (Active
LOW)
Register Clock
Register Counter Selector
Enable Input
Load Counter (Active
LOW)
Data Outputs
Load Counter (Active
HIGH)
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOL
INPUT AND OUTPUT EQUIVALENT CIRCUIT
HC696
HC697
HC698
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HC699



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M54/M74HC696/697/698/699
TRUTH TABLE
INPUTS
OUTPUTS
CCLR LOAD ENP ENT CCK U/D RCK R/C G QA QB QC QD
X X X X X X X XHZ Z Z Z
L X X X X (*) X X L L L L L L
HLXX
HHHX
X X LLa b c d
X X LL
NO CHANGE
HHXH
X X LL
NO CHANGE
HHL L
H X LL
COUNT UP
HHL L
L X LL
COUNT DOWN
H XX X
X X LL
NO CHANGE
X XX XX X
H L a’ b’ c’ d’
X
(*)
X
Z
a-d
a’-d’
XX XX X
HL
NO CHANGE
: For HC698/699
: Don’t care
: High impedance
: The level of steady state input at inputs a through D respectively
: The level of steady state outputs at internal counter outputs QA’ through QD’ respectively
RCO function : HC696/8 - RCO = (UP QA QD ENT + UP QA QD ENT)
HC697/9 - RCO = (UP QA QB QC QD ENT + UP QA QB QC QD ENT)
FUNCTION
HIGH IMPEDANCE
CLEAR COUNTER
LOAD COUNTER
NO COUNT
NO COUNT
COUNT UP
COUNT DOWN
NO COUNT
LOAD REGISTER
NO LOAD
BLOCK DIAGRAM
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M54/M74HC696/697/698/699
LOGIC DIAGRAM (HC696)
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74HC699 pdf

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