74HC40105 Datasheet PDF - NXP

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74HC40105
NXP

Part Number 74HC40105
Description 4-bit x 16-word FIFO register
Page 30 Pages


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74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 4 — 29 January 2016
Product data sheet
1. General description
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Input levels:
For 74HC40105: CMOS level
For 74HCT40105: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C



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NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74HC40105D 40 C to +125 C
74HCT40105D
74HC40105DB 40 C to +125 C
74HCT40105DB
74HC40105PW 40 C to +125 C
Name
SO16
SSOP16
TSSOP16
4. Functional diagram
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1

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Fig 1. Logic symbol
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Fig 2. IEC logic symbol
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 36



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NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
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Fig 3. Functional diagram
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Fig 4.
LOW on S input of FF1 and FF5 sets Q output to HIGH independent of state on R input.
LOW on R input of FF2, FF3 and FF4 sets Q output to LOW independent of state on S input.
Logic diagram

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74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 36



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NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
5. Pinning information
5.1 Pinning
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Fig 5. Pin configuration SO16
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Fig 6. Pin configuration (T)SSOP16
5.2 Pin description
Table 2. Pin description
Symbol
Pin
OE 1
DIR 2
SI 3
D0 to D3
4, 5, 6, 7
GND
8
MR 9
Q0 to Q3
13, 12, 11, 10
DOR
14
SO 15
VCC 16
Description
output enable input (active LOW)
data-in-ready output
shift-in input (LOW-to-HIGH, edge triggered)
parallel data input
ground (0 V)
asynchronous master-reset input (active HIGH)
data output
data-out-ready output
shift-out input (HIGH-to-LOW, edge triggered)
supply voltage
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 36



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