74AUP1T97 Datasheet PDF - Fairchild Semiconductor

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74AUP1T97
Fairchild Semiconductor

Part Number 74AUP1T97
Description Low Power Configurable Gate
Page 11 Pages


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October 2010
74AUP1T97
TinyLogic® Low Power Configurable Gate with
Voltage-Level Translator
Features
ƒ Single Supply Voltage Translator
- 1.8V to 3.3V Input at VCC=3.3V
- 1.8V to 2.5V Input at VCC=2.5V
ƒ 2.3V to 3.6V VCC Supply Voltage Operation
ƒ 3.6V Over-Voltage Tolerant I/O’s at VCC from
2.3V to 3.6V
ƒ Power-Off High-Impedance Inputs and Outputs
ƒ Low Static Power Consumption
- ICC=0.9µA Maximum
ƒ Low Dynamic Power Consumption
- CPD=2.7pF Typical at 3.3V
ƒ Ultra-Small MicroPak™ Packages
Description
The 74AUP1T97 is a universal configurable 2-input
logic gate that provides single supply voltage level
translation. This device is designed for applications with
inputs switching levels that accept 1.8V low voltage
CMOS signals while operating from either a single 2.5V
or 3.3V supply voltage. The 74AUP1T97 is an ideal low
power solution for mixed voltage signal applications
especially for battery-powered portable applications.
This product guarantees very low static and dynamic
power consumption across entire voltage range. All
inputs are implemented with hysteresis to allow for
slower transition input signals and better switching
noise immunity.
The 74AUP1T97 provides for multiple functions as
determined by various configurations of the three
inputs. The potential logic functions provided are MUX,
AND, NAND, OR, and NOR, inverter and buffer. Refer
to Figures 3 to 9.
Ordering Information
Part Number Top Mark
Package
74AUP1T97L6X
AH 6-Lead MicroPak™, 1.0mm Wide
74AUP1T97FHX
AH 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Packing Method
5000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1T97 • Rev. 1.0.3
www.fairchildsemi.com



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Logic Diagram
3
A
1
B
6
C
Figure 1. Logic Diagram (Positive Logic)
Pin Configurations
B1
GND 2
A3
6C
5 VCC
4Y
Figure 2. MicroPak™ (Top Through View)
4Y
Pin Definitions
Pin #
1
2
3
4
5
6
Name
B
GND
A
Y
VCC
C
Description
Data Input
Ground
Data Input
Output
Supply Voltage
Data Input
© 2008 Fairchild Semiconductor Corporation
74AUP1T97 • 1.0.3
2
www.fairchildsemi.com



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Function Table
Inputs
CB
LL
LL
LH
LH
HL
HL
HH
HH
H = HIGH Logic Level
L = LOW Logic Level
A
L
H
L
H
L
H
L
H
Function Selection Table
Logic Function
2-to-1 MUX
2-Input AND Gate
2-Input OR Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input AND Gate with One Inverted Input
2-Input NOR Gate with One Inverted Input
2-Input OR Gate
Inverter
Buffer
74AUPIT97
Y=Output
L
L
H
H
L
H
L
H
Connection Configuration
Figure 3
Figure 4
Figure 5
Figure 5
Figure 6
Figure 6
Figure 7
Figure 8
Figure 9
© 2008 Fairchild Semiconductor Corporation
74AUP1T97 • 1.0.3
3
www.fairchildsemi.com



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74AUP1T97 Logic Configurations
Figure 3 through Figure 9 show the logical functions
that can be implemented using the 74AUP1T97. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should
be connected.
C
B1
6
BY
25
A
A3
4
GND
Note:
1. When C is L, Y=B.
2. When C is H, Y=A.
Figure 3. 2-to-1 MUX
VCC
C
Y
VCC
C 1 6C
Y
A
25
A3
4Y
GND
Figure 4. 2-Input AND Gate
VCC
VCC
C
C
Y
Y
B
A
B1
6C
1 6C
C
25
C 25
A
Y
A3
4Y
Y
B
3 4Y
GND
GND
Figure 5. Input OR Gate with One Inverted Input Figure 6. 2-Input AND Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input NOR Gate with One Inverted Input
VCC
C
YB
1 6C
B 25
3 4Y
GND
Figure 7. 2-Input OR Gate
C
VCC
1 6C
Y 25
3 4Y
GND
Figure 8. Inverter
VCC
B
© 2008 Fairchild Semiconductor Corporation
74AUP1T97 • 1.0.3
B1
6
Y 25
3 4Y
GND
Figure 9. Buffer
4
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