74ALVCH16374 Datasheet PDF - Philips

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74ALVCH16374
Philips

Part Number 74ALVCH16374
Description 16-bit edge-triggered D-type flip-flop
Page 12 Pages


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INTEGRATED CIRCUITS
74ALVCH16374
2.5V/3.3V 16-bit edge-triggered D-type
flip-flop (3-State)
Product specification
Supersedes data of 1997 Mar 21
IC24 Data Handbook
1998 Jun 18
Philips
Semiconductors



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Philips Semiconductors
16-bit edge-triggered D-type flip-flop (3-State)
Product specification
74ALVCH16374
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
All data inputs have bushold
Output drive capability 50transmission lines @ 85°C
Current drive ±24 mA at 3.0 V
DESCRIPTION
The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. The 74ALVCH16374 consists of 2 sections of eight
edge-triggered flip-flops. A clock (CP) input and an output enable
(OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
SW00074
TYPICAL
tPHL/tPLH
Propagation delay
CP to Qn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
fMAX
Maximum clock frequency
VCC = 2.5V
VCC = 3.3V
CI Input capacitance
CPD Power dissipation capacitance per flip-flop VI = GND to VCC1
Outputs enabled
Outputs disabled
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
2.3
2.4
300
350
5.0
16
10
UNIT
ns
MHz
MHz
pF
pF
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH16374 DL
–40°C to +85°C
74ALVCH16374 DGG
NORTH AMERICA
ACH16374 DL
ACH16374 DGG
DWG NUMBER
SOT370-1
SOT362-1
1998 Jun 18
2 853-2073 19604



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Philips Semiconductors
16-bit edge-triggered D-type flip-flop (3-State)
Product specification
74ALVCH16374
PIN DESCRIPTION
PIN NUMBER SYMBOL
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17,
19, 20, 22, 23
1Q0 to 1Q7
GND
VCC
2Q0 to 2Q7
24 2OE
25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
48
2CP
2D0 to 2D7
1D0 to 1D7
1CP
NAME AND FUNCTION
Output enable input
(active LOW)
3-State flip-flop outputs
Ground (0V)
Positive supply voltage
3-State flip-flop outputs
Output enable input
(active LOW)
Clock input
Data inputs
Data inputs
Clock input
LOGIC DIAGRAM
1D0
DQ
CP
FF1
1Q0
LOGIC SYMBOL
1 24
1OE 2OE
47 1D0
1Q0
46 1D1
44 1D2
1Q1
1Q2
43 1D3
41 1D4
1Q3
1Q4
40 1D5
38 1D6
1Q5
1Q6
37 1D7
1Q7
36 2D0
2Q0
35 2D1
2Q1
33 2D2
2Q2
32 2D3
2Q3
30 2D4
2Q4
29 2D5
2Q5
27 2D6
2Q6
26 2D7
2Q7
1CP 2CP
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
48 25
SW00075
2D0
DQ
2Q0
CP
FF9
1CP
1OE
2CP
2OE
TO 7 OTHER CHANNELS
FUNCTION TABLE
OPERATING MODES
INPUTS
OE CP
Load and read register
L°
L°
Load register and disable outputs
H
H
°
°
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high impedance OFF-state
° = LOW-to-HIGH CP transition
TO 7 OTHER CHANNELS
SW00076
INTERNAL
OUTPUTS
Dn
FLIP-FLOPS
Q0 to Q7
l LL
h HH
l LZ
h HZ
1998 Jun 18
3



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Philips Semiconductors
16-bit edge-triggered D-type flip-flop (3-State)
Product specification
74ALVCH16374
LOGIC SYMBOL (IEEE/IEC)
1OE
1CLK
2OE
2CLK
1
48
24
25
1D0 47
1D1 46
1D2 44
43
1D3
1D4 41
1D5 40
1D6 38
1D7 37
2D0 36
2D1 35
2D2 33
2D3 32
2D4 30
29
2D5
2D6 27
2D7 26
1EN
C1
2EN
C2
1D
1
2D 2
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
11 1Q6
12 1Q7
13 2Q0
14 2Q1
16 2Q2
17 2Q3
19 2Q4
20 2Q5
22 2Q6
23 2Q7
SW00199
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
VCC DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC supply voltage (for low-voltage applications)
VI
VO
Tamb
tr, tf
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
BUS HOLD CIRCUIT
VCC
Data Input
To internal circuit
SW00044
CONDITIONS
For data input pins
For control pins
VCC = 2.3 to 3.0V
VCC = 3.0 to 3.6V
LIMITS
MIN MAX
2.3 2.7
3.0 3.6
1.2 3.6
0 VCC
0 5.5
0 VCC
–40 +85
0 20
0 10
UNIT
V
V
V
°C
ns/V
1998 Jun 18
4



74ALVCH16374 datasheet pdf
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74ALVCH16374 pdf
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