74ACT259 Datasheet PDF - ETC


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74ACT259
ETC

Part Number 74ACT259
Description 8-Bit Addressable Latch
Page 11 Pages

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MC74AC259, MC74ACT259
8−Bit Addressable Latch
The MC74AC259/74ACT259 is a high−speed 8−bit addressable
latch designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing single line
data in eight addressable latches, and also a 1−of−8 decoder and
demultiplexer with active HIGH outputs. The device also incorporates
an active LOW Common Clear for resetting all latches, as well as an
active LOW Enable. It is functionally identical to the ALS259 8−bit
addressable latch.
Serial−to−Parallel Conversion
Eight Bits of Storage with Output of Each Bit Available
Random (Addressable) Data Entry
Active High Demultiplexing or Decoding Capability
Easily Expandable
Common Clear
Pb−Free Packages are Available
VCC MR E
D Q7 Q6 Q5 Q4
16 15 14 13 12 11 10 9
12345678
A0 A1 A2 Q0 Q1 Q2 Q3 GND
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
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16
1
16
1
16
1
PDIP−16
N SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
M, MEL SUFFIX
CASE 966
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
A0 E D
A1
A2 MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 2. Logic Symbol
MODE SELECT TABLE
E MR
Mode
L H Addressable Latch
H H Memory
L L Active HIGH 8−Channel Demultiplexer
H L Clear
H = HIGH Voltage Level
L = LOW Voltage Level
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 6
1
Publication Order Number:
MC74AC259/D



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MC74AC259, MC74ACT259
MODE SELECT−FUNCTION TABLE
Operating
Inputs
Outputs
Mode
MR E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Master Reset L H X X X X L L L L L L L L
L L d L L L Q=d L L L L L L L
L L d H L L L Q=d L L L L L L
Demultiplex L L d L H L L L Q = d L L L L L
(Active HIGH
Decoder when
D = H)
•••••• • • • • • • • •
L L d H H H L L L L L L L Q=d
Store
(Do Nothing)
H H X X X X q0
q1
q2
q3
q4
q5
q6
q7
H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7
H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7
Addressable
Latch
H L d LHL
• •••••
q0
q1 Q = d q3
•••
q4
q5
q6
q7
•••••• • • • • • • • •
•••••• • • • • • • • •
H L d H H H q0 q1 q2 q3 q4 q5 q6 Q = d
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW−to−HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed
or cleared.
FUNCTIONAL DESCRIPTION
The MC74AC259/74ACT259 has four modes of
operation as shown in the Mode Selection Table. In the
addressable latch mode, data on the Data line (D) is written
into the addressed latch. The addressed latch will follow the
data input with all non−addressed latches remaining in their
previous states in the memory mode. All latches remain in
their previous state and are unaffected by the Data or
Address inputs.
In the one−of−eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other outputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the MC74AC/ACT259 as an addressable
latch, changing more than one bit of the address could
impose a transient wrong address. Therefore, this should
only be done while in the memory mode. The Mode Select
Function Table summarizes the operations of the
MC74AC/ACT259.
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MC74AC259, MC74ACT259
Q7
Q6
Q5
MR
Q4
A2 Q3
A1
A0 Q2
Q1
D
E
Q0
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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MC74AC259, MC74ACT259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
VIN DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
IIN DC Input Current, per Pin
±20 mA
IOUT
DC Output Sink/Source Current, per Pin
±50 mA
ICC DC VCC or GND Current per Output Pin
±50 mA
Tstg Storage Temperature
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Typ Max
VCC Supply Voltage
AC
ACT
2.0 5.0 6.0
4.5 5.0 5.5
VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND)
0 − VCC
tr, tf
Input Rise and Fall Time (Note 1)
AC Devices except Schmitt Inputs
VCC @ 3.0 V
150
VCC @ 4.5 V
40
VCC @ 5.5 V
25
tr, tf
Input Rise and Fall Time (Note 2)
ACT Devices except Schmitt Inputs
VCC @ 4.5 V
10
VCC @ 5.5 V
8.0
TJ Junction Temperature (PDIP)
− − 140
TA Operating Ambient Temperature Range
−40 25
85
IOH Output Current − High
− − −24
IOL Output Current − Low
− − 24
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
Unit
V
V
ns/V
ns/V
°C
°C
mA
mA
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