68HC705BD7 Datasheet PDF - Freescale Semiconductor

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68HC705BD7
Freescale Semiconductor

Part Number 68HC705BD7
Description SPECIFICATION REV 2.0 (General Release)
Page 30 Pages


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Freescale Semiconductor, Inc.
HC05BD7GRS/H
www.RDaEtaSVhee2t4.U0.com
68HC05BD7
68HC705BD7
68HC05BD2
SPECIFICATION
REV 2.0
(General Release)
© January 20, 1998
Technical Operation Taiwan
Taipei, Taiwan
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Freescale Semiconductor, Inc.
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MC68HC05BD7 RevF. 2r.e0escale SemicondGuEcNtoERr,AILnRcE.LEASE SPECIFICATION
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TABLE OF CONTENTS
SECTION 1 GENERAL DESCRIPTION .............................................. 1
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.3.1
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.2.10
1.2.11
1.2.12
1.2.13
1.3
Features...................................................................................... 1
Hardware Features................................................................1
Software Features .................................................................3
Signal Description.......................................................................7
VDD and VSS........................................................................7
IRQ/VPP ................................................................................ 7
EXTAL, XTAL ........................................................................7
Crystal Oscillator..............................................................7
RESET ..................................................................................8
PA0-PA7................................................................................ 8
PB0-PB5................................................................................ 8
PC0*/PWM8*-PC1*/PWM9* ..................................................8
PC2/PWM10/ADC0- PC5/PWM13/ADC3 .............................8
PC6/PWM14/VSYNO, PC7/PWM15/HSYNO .......................8
PD0*/SDA*, PD1*/SCL* ........................................................8
PD2***/CLAMP, PD3*/SOG ..................................................8
PWM0**-PWM7** ..................................................................9
HSYNC, VSYNC ...................................................................9
Options .......................................................................................9
SECTION 2
2.1
2.2
2.3
2.4
MEMORY ....................................................................... 11
COP ..........................................................................................15
ROM .........................................................................................15
EPROM..................................................................................... 15
RAM .......................................................................................... 15
SECTION 3 CPU CORE..................................................................... 17
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.5.1
3.1.5.2
3.1.5.3
3.1.5.4
3.1.5.5
Registers................................................................................... 17
Accumulator (A)...................................................................17
Index Register (X) ...............................................................18
Stack Pointer (SP)...............................................................18
Program Counter (PC) ........................................................18
Condition Code Register (CCR) ..........................................18
Half Carry Bit (H-Bit) ......................................................19
Interrupt Mask (I-Bit) ......................................................19
Negative Bit (N-Bit) ........................................................19
Zero Bit (Z-Bit) ...............................................................19
Carry/Borrow Bit (C-Bit) .................................................19
SECTION 4
4.1
4.2
4.3
INTERRUPTS................................................................. 21
CPU Interrupt Processing .........................................................21
Reset Interrupt Sequence.........................................................23
Software Interrupt (SWI) ...........................................................23
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GENERAL RELEASE SPEFCrIeFeICsAcTaIOlNe Semiconductor, MInCc68. HC05BD7 Rev. 2.0
4.4
4.4.1
4.4.2
4.4.3
4.4.4
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Hardware Interrupts.................................................................. 23
External Interrupt (IRQ)....................................................... 23
VSYNC Interrupt ................................................................. 24
DDC12AB Interrupt ............................................................. 24
Multi-Function Timer Interrupt (MFT) .................................. 25
SECTION 5 RESETS..........................................................................27
5.1
5.2
5.2.1
5.2.2
5.2.3
External Reset (RESET) .......................................................... 27
Internal Resets ......................................................................... 27
Power-On Reset (POR) ...................................................... 27
Computer Operating Properly Reset (COPR)..................... 27
Illegal Address (ILADR) Reset ............................................ 28
SECTION 6 OPERATING MODES ....................................................29
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
User Mode................................................................................ 29
SELF-CHECK MODE............................................................... 29
Bootstrap Mode ........................................................................ 29
Mode Entry ............................................................................... 29
EPROM Programming.............................................................. 30
Programming Sequence ..................................................... 30
Programming Control Register (PCR) ................................ 31
Low Power Modes.................................................................... 31
STOP Instruction................................................................. 31
WAIT Instruction ................................................................. 31
COP Watchdog Timer Considerations ..................................... 32
SECTION 7
7.1
7.2
7.3
7.4
7.5
7.6
INPUT/OUTPUT PORTS ................................................33
Port A ....................................................................................... 33
Port B ....................................................................................... 33
Port C ....................................................................................... 33
Port D ....................................................................................... 33
Input/Output Programming ....................................................... 34
Port C and D Configuration Register........................................ 35
SECTION 8
8.1
8.2
PULSE WIDTH MODULATION......................................37
Operation of 8-Bit PWM ........................................................... 37
Open-Drain Option Register..................................................... 38
SECTION 9 DDC12AB INTERFACE .................................................39
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Introduction............................................................................... 39
DDC12AB Features.................................................................. 39
Registers .................................................................................. 40
DDC Address Register (DADR) .......................................... 40
DDC Control Register (DCR) .............................................. 40
DDC Master Control Register (DMCR) ............................... 41
DDC Status Register (DSR)................................................ 43
DDC Data Transmit Register (DDTR)................................. 44
Page ii
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