68HC05PD6 Datasheet PDF - Freescale Semiconductor


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68HC05PD6
Freescale Semiconductor

Part Number 68HC05PD6
Description SPECIFICATION (General Release)
Page 30 Pages

68HC05PD6 datasheet pdf
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REV 1.1
68HC05PD6
68HC705PD6
SPECIFICATION
(General Release)
© July 7, 1997
Technical Operations Taiwan
Asia Pacific Semiconductor Products Group
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
© Motorola, Inc., 1997



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July 7, 1997
GENERAL RELEASE SPECIFICATION
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Section
TABLE OF CONTENTS
Title
Page
SECTION 1
GENERAL DESCRIPTION
1.1 FEATURES ...................................................................................................... 1-1
1.2 MASK OPTIONS.............................................................................................. 1-2
1.3 SIGNAL DESCRIPTION .................................................................................. 1-4
1.3.1 VDD and VSS .............................................................................................. 1-4
1.3.2 OSC2, OSC1 ............................................................................................... 1-5
1.3.3 XOSC2, XOSC1 .......................................................................................... 1-5
1.3.4 RESET......................................................................................................... 1-6
1.3.5 VPP.............................................................................................................. 1-6
1.3.6 PA0-PA7 ...................................................................................................... 1-6
1.3.7 PB0/KWI0-PB7/KWI7 .................................................................................. 1-6
1.3.8 PC0/RDI, PC1/TDO ..................................................................................... 1-6
1.3.9 PC2/TCMP, PC3/TCAP ............................................................................... 1-7
1.3.10 PC4/EVI, PC5/EVO ..................................................................................... 1-7
1.3.11 PC6/IRQ2, PC7/IRQ1 .................................................................................. 1-7
1.3.12 BP0/PD0-BP3/PD3 ...................................................................................... 1-7
1.3.13 FP32/PD4-FP35/PD7 .................................................................................. 1-7
1.3.14 FP24/PE0-FP31/PE7................................................................................... 1-7
1.3.15 FP16/PF0-FP23/PF7 ................................................................................... 1-8
1.3.16 FP8/PG0-FP15/PG7 .................................................................................... 1-8
1.3.17 FP0/PH0-FP7/PH7 ...................................................................................... 1-8
1.3.18 VLCD3 ......................................................................................................... 1-8
1.3.19 BS1-BS3 ...................................................................................................... 1-8
1.3.20 DIN............................................................................................................... 1-8
SECTION 2
MEMORY
2.1 MEMORY MAP ................................................................................................ 2-1
2.2 ROM................................................................................................................. 2-2
2.3 RAM ................................................................................................................. 2-2
2.4 I/O AND CONTROL REGISTERS ................................................................... 2-2
SECTION 3
CENTRAL PROCESSING UNIT
3.1 REGISTERS .................................................................................................... 3-1
3.2 ACCUMULATOR (A)........................................................................................ 3-2
3.3 INDEX REGISTER (X) ..................................................................................... 3-2
3.4 STACK POINTER (SP) .................................................................................... 3-2
3.5 PROGRAM COUNTER (PC) ........................................................................... 3-3
3.6 CONDITION CODE REGISTER (CCR) ........................................................... 3-3
3.6.1 Half Carry Bit (H-Bit) .................................................................................... 3-3
3.6.2 Interrupt Mask (I-Bit) .................................................................................... 3-3
MC68HC05PD6
REV 1.1
MOTOROLA
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GENERAL RELEASE SPECIFICATION
July 7, 1997
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Section
TABLE OF CONTENTS
Title
Page
3.6.3
3.6.4
3.6.5
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-4
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
SECTION 4
INTERRUPTS
4.1 CPU INTERRUPT PROCESSING ................................................................... 4-1
4.2 RESET INTERRUPT SEQUENCE .................................................................. 4-3
4.3 SOFTWARE INTERRUPT (SWI) ..................................................................... 4-3
4.4 HARDWARE INTERRUPTS ............................................................................ 4-4
4.4.1 P-Decoder Interrupt (PDI)............................................................................ 4-4
4.4.2 IRQ1 and IRQ2 ............................................................................................ 4-4
4.4.3 Key Wake-up Interrupt (KWI)....................................................................... 4-6
4.4.4 Timer Interrupt ............................................................................................. 4-7
4.4.5 Serial Communication Interface (SCI) ......................................................... 4-7
4.4.6 Real Time Clock Interrupt (RTC) ................................................................. 4-7
4.4.7 Interrupt Control Register (INTCR) .............................................................. 4-7
4.4.8 Interrupt Status Register (INTSR)................................................................ 4-8
4.4.9 Key Wake-Up Input Enable Register (KWIEN)............................................ 4-9
SECTION 5
RESETS
5.1 EXTERNAL RESET (RESET).......................................................................... 5-1
5.2 INTERNAL RESETS ........................................................................................ 5-2
5.2.1 Power-On Reset (POR) ............................................................................... 5-2
5.2.2 Computer Operating Properly Reset (COPR).............................................. 5-2
5.2.3 Illegal Address Reset (ILADR)..................................................................... 5-2
SECTION 6
LOW POWER MODES
6.1 SINGLE-CHIP (NORMAL) MODE.................................................................... 6-1
6.2 SELF-CHECK MODE....................................................................................... 6-1
6.3 LOW-POWER MODES .................................................................................... 6-1
6.3.1 STOP Instruction ......................................................................................... 6-2
6.3.2 WAIT Instruction .......................................................................................... 6-2
SECTION 7
INPUT/OUTPUT PORTS
7.1 PORT A............................................................................................................ 7-1
7.2 PORT B............................................................................................................ 7-1
7.3 PORT C............................................................................................................ 7-2
7.4 PORT D............................................................................................................ 7-3
7.4.1 Port D MUX Register (PDMUX)................................................................... 7-4
MOTOROLA
ii
MC68HC05PD6
REV 1.1




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