5962-89841 Datasheet PDF - Cypress Semiconductor

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5962-89841
Cypress Semiconductor

Part Number 5962-89841
Description Flash-erasable Reprogrammable CMOS PAL Device
Page 13 Pages


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PALCE22V10 is a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Flash-erasable Reprogrammable
CMOS PAL® Device
Features
Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
• Variable product terms
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
• Up to 22 input terms and 10 outputs
Logic Block Diagram (PDIP/CDIP)
VSS I I I I
12 11
10
9
8
I
7
• DIP, LCC, and PLCC available
— 5 ns commercial version
4 ns tCO
3 ns tS
5 ns tPD
181-MHz state machine
— 10 ns military and industrial versions
7 ns tCO
6 ns tS
10 ns tPD
110-MHz state machine
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
• High reliability
— Proven Flash EPROM technology
— 100% programming and functional testing
II
I I I CP/I
6 5 4 3 21
PROGRAMMABLE
AND ARRAY
(132 X 44)
8 10 12 14 16 16 14 12 10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13 14 15
I I/O9 I/O8
Pin Configuration
16 17
I/O 7
I/O6
LCC
Top View
18
I/O5
4 3 2 1 282726
I5
I6
25 I/O2
24 I/O3
I7
NC 8
23 I/O4
22 N/C
I9
I 10
21 I/O5
20 I/O6
I 11
19 I/O7
12131415161718
19 20 21 22
I/O4 I/O3 I/O2 I/O1
PLCC
Top View
4 3 2 1 2827 26
I5
25
I6
24
I7
23
NC 8
22
I9
21
I 10
20
I 11 121314 1516 1718 19
I/O2
I/O3
I/O4
N/C
I/O5
I/O6
I/O7
23 24
I/O0 VCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03027 Rev. *B
Revised April 9, 2004



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USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Selection Guide
Generic Part Number
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
tPD ns
Com’l Mil/Ind
5
7.5
10 10
15 15
25 25
tS ns
Com’l Mil/Ind
3
5
66
10 10
15 15
tCO ns
Com’l Mil/Ind
4
5
77
88
15 15
ICC mA
Com’l Mil/Ind
130
130
90 150
90 120
90 120
Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-products (AND-OR)
logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and
provides up to 22 inputs and 10 outputs. The PALCE22V10
can be electrically erased and reprogrammed. The program-
mable macrocell provides the capability of defining the archi-
tecture of each output individually. Each of the ten potential
outputs may be specified as “registered” or “combinatorial.”
Polarity of each output may also be individually selected,
allowing complete flexibility of output configuration. Further
configurability is provided through “array” configurable “output
enable” for each potential output. This feature allows the 10
outputs to be reconfigured as inputs on an individual basis, or
alternately used as a combination I/O controlled by the
programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the
PALCE22V10 is optimized to the configurations found in a
majority of applications without creating devices that burden
the product term structures with unusable product terms and
lower performance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, elimi-
nating the need to dedicate standard product terms for initial-
ization functions. The device automatically resets upon
power-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array
complexity. Since each of the ten output pins may be individ-
ually configured as inputs on a temporary or permanent basis,
functions requiring up to 21 inputs and only a single output and
down to twelve inputs and ten outputs are possible. The ten
potential outputs are enabled using product terms. Any output
pin may be permanently selected as an output or arbitrarily
enabled as an output and an input through the selective use
of individual product terms associated with each output. Each
of these outputs is achieved through an individual program-
mable macrocell. These macrocells are programmable to
provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the
register is fed back into the array, providing current status
information to the array. This information is available for estab-
lishing the next result in applications such as control state
machines. In a combinatorial configuration, the combinatorial
output or, if the output is disabled, the signal present on the I/O
pin is made available to the array. The flexibility provided by
both programmable product term control of the outputs and
variable product terms allows a significant gain in functional
density through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash
reprogrammability.
Configuration Table
Registered/Combinatorial
C1 C0
00
Configuration
Registered/Active LOW
01
Registered/Active HIGH
10
Combinatorial/Active LOW
11
Combinatorial/Active HIGH
Document #: 38-03027 Rev. *B
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Macrocell
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
AR
DQ
OUTPUT
SELECT
MUX
CP Q
S1 S0
SP
INPUT/
FEEDBACK
MUX
S1
C1
C0 MACROCELL
Document #: 38-03027 Rev. *B
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USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 16 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current..................................................... > 200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................ >2001V
Operating Range
Range
Commercial
Industrial
Military[1]
Ambient
Temperature
0°C to +75°C
–40°C to +85°C
–55°C to +125°C
VCC
5V ±5%
5V ±10%
5V ±10%
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
VOH
VOL
VIH
VIL[4]
IIX
IOZ
ISC
ICC1
ICC2[6]
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
VCC = Min.,
VIN = VIH or VIL
IOH = –3.2 mA
IOH = –2 mA
Com’l
Mil/Ind
VCC = Min.,
VIN = VIH or VIL
IOL = 16 mA
IOL = 12 mA
Com’l
Mil/Ind
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
Input Leakage Current
VSS < VIN < VCC, VCC = Max.
Output Leakage Current
VCC = Max., VSS < VOUT < VCC
Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6]
Standby Power Supply
Current
VCC = Max.,
VIN = GND,
Outputs Open in Unprogrammed
Device
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Com’l
Mil/Ind
Operating Power Supply
Current
VCC = Max., VIL = 0V, VIH = 3V, 10, 15, 25 ns
Output Open, Device Programmed
as a 10-bit Counter,
5, 7.5 ns
f = 25 MHz
15, 25 ns
10 ns
Com’l
Com’l
Mil/Ind
Mil/Ind
Min. Max. Unit
2.4 V
0.5 V
2.0 V
–0.5 0.8 V
–10 10 µA
–40 40 µA
–30 –130 mA
90 mA
130 mA
120 mA
120 mA
110 mA
140 mA
130 mA
130 mA
Capacitance[6]
Parameter
Description
CIN
COUT
Input Capacitance
Output Capacitance
Endurance Characteristics[6]
Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
Min.
Max.
10
10
Unit
pF
pF
Parameter
Description
Test Conditions
Min. Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions 100
Cycles
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to –3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03027 Rev. *B
Page 4 of 13



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