56F8023 Datasheet PDF - Freescale Semiconductor


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56F8023
Freescale Semiconductor

Part Number 56F8023
Description 16-bit Digital Signal Controllers
Page 30 Pages

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56F8033/56F8023
Data Sheet
Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8023
Rev. 6
02/2010
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Version History
Rev. 0
Rev. 1
Rev. 2
Rev. 3
Rev. 4
Rev. 5
Document Revision History
Description of Change
Initial public release.
• In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby
mode from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-20 as follows:
Old values: 1 μs typical, 2 μs maximum
New values: 35 ns typical, 45 ns maximum
In Table 10-19, changed the maximum ADC internal clock frequency from 8 MHz to 5.33
MHz.
• Added the following note to the description of the TMS signal in Table 2-3:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Corrected pin number labels in Figure 11-1 as follows:
Old labels: Pin 1, Pin 12, Pin 23, Pin 34
New labels: Pin 1, Pin 9, Pin 17, Pin 25
• Changed the ITCN_BASE address In Table 5-3 (was $00 F060, is $00 F0E0).
• Changed the VBA register reset value and updated the footnote in Section 5.6.8.
• Changed the STANDBY > STOP IDD values in Table 10-6 as follows:
Typical: was 290μA, is 540μA
Maximum: was 390μA, is 650μA
• Changed the POWERDOWN IDD values in Table 10-6 as follows:
Typical: was 190μA, is 440μA
Maximum: was 250μA, is 550μA
• Changed footnote 1 in Table 10-12 (was “Output frequency after application of 8MHz
trim value, at 125°C.”, is “Output frequency after application of factory trim”).
• Deleted the text “at 125°C” from Figure 10-5.
• Changed the maximum input offset voltage in Table 10-20 (was +/- 20 mV, is ±35 mV).
• Revised Section 7, Security Features.
• Fixed miscellaneous typos.
56F8033/56F8023 Data Sheet, Rev. 6
2 Freescale Semiconductor



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Version History
Rev. 6
Document Revision History
Description of Change
In the table Recommended Operating Conditions, removed the line “XTAL not driven by
an external clock“ from the characteristic
“Oscillator Input Voltage High
XTAL not driven by an external clock
XTAL driven by an external clock source”
Added 56F8033 device to document
Removed “Preliminary” from data sheet
In the System Integration Module (SIM) chapter, fixed typos
Please see http://www.freescale.com for the most current data sheet revision.
Freescale Semiconductor
56F8033/56F8023 Data Sheet, Rev. 6
3



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56F8033/56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8033 offers 64KB (32K x 16) Program Flash
• 56F8023 offers 32KB (16K x 16) Program Flash
• 56F8033 offers 8KB (4K x 16) Unified Data/Program
RAM
• 56F8023 offers 4KB (2K x 16) Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET or
GPIOA
4
VCAP
VDD
VSS
2
VDDA VSSA
5 PWM
or TMRA or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
DAC
4 AD0
ADC
or CMP
or GPIOC
4 AD1
Memory
Program Memory
16K x 16 Flash
32K x 16 Flash
Unified Data /
Program RAM
2K x 16
4K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I2C
or CMP
or GPIOB
QSPI
or PWM
or I2C
or TMRA
or GPIOB
QSCI
or PWM
or I2C
or TMRA
or GPIOB
24
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8033/56F8023 Block Diagram
56F8033/56F8023 Data Sheet, Rev. 6
4 Freescale Semiconductor




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