46V16M8 Datasheet PDF - Micron Technology

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46V16M8
Micron Technology

Part Number 46V16M8
Description MT46V16M8
Page 30 Pages


46V16M8 datasheet pdf
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DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
www.DataSheetr4eUc.ceoivmed with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
MARKING
32M4
16M8
8M16
• Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
TG
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)1
7.5ns @ CL = 2.5 (DDR266B)2
10ns @ CL = 2 (DDR200)3
-75Z
-75
-8
• Self Refresh
Standard
Low Power
none
L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4 x8 x16
VDD
VDD
VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VssQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VssQ
NC NC DQ7
NC NC NC
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD
VDD
VDD
NC DNU DNU
NC NC LDM
WE# WE# WE#
CAS# CAS# CAS#
RAS# RAS# RAS#
CS# CS# CS#
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
x16 x8
x4
66 VSS
VSS VSS
65 DQ15 DQ7 NC
64 VSSQ VSSQ VSSQ
63 DQ14 NC NC
62 DQ13 DQ6 DQ3
61 VDDQ VDDQ VDDQ
60 DQ12 NC NC
59 DQ11 DQ5 NC
58 VSSQ VSSQ VSSQ
57 DQ10 NC NC
56 DQ9 DQ4 DQ2
55 VDDQ VDDQ VDDQ
54 DQ8 NC NC
53 NC
NC NC
52 VSSQ VSSQ VSSQ
51 UDQS DQS DQS
50 DNU DNU DNU
49
VREF
VREF
VREF
48 VSS
VSS VSS
47 UDM DM DM
46 CK# CK# CK#
45 CK
CK CK
44 CKE CKE CKE
43 NC
NC NC
42 NC
NC NC
41 A11 A11 A11
40 A9
A9 A9
39 A8
A8 A8
38 A7
A7 A7
37 A6
A6 A6
36 A5
A5 A5
35 A4
A4 A4
34 VSS
VSS VSS
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K(A0–A11)
4 (BA0, BA1)
2K(A0–A9,A11)
16 Meg x 8
8 Meg x 16
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K 4K
4K(A0–A11)
4K(A0–A11)
4 (BA0, BA1)
4 (BA0, BA1)
1K(A0–A9)
512(A0–A8)
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
DATA-OUT ACCESS DQS-DQ
GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW
-75Z 133 MHz
-75 100 MHz
-8 100 MHz
133 MHz
133 MHz
125 MHz
2.5ns
2.5ns
3.4ns
±0.75ns
±0.75ns
±0.8ns
+0.5ns
+0.5ns
+0.6ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.



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128MB DDR SDRAM PART NUMBERS
(Note: xx= -75, -75Z, or -8)
PART NUMBER
MT46V32M4TG-xx
MT46V32M4TG-xxL
MT46V16M8TG-xx
MT46V16M8TG-xxL
MT46V8M16TG-xx
www.DataSheeMt4TU4.c6oVm8M16TG-xxL
CONFIGURATION
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
I/O DRIVE LEVEL
Full Drive
Full Drive
Full Drive
Full Drive
Programmable Drive
Programmable Drive
REFRESH OPTION
Standard
Low Power
Standard
Low Power
Standard
Low Power
GENERAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-
bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 128Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compatible.
NOTE 1:
NOTE 2:
The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
Throughout the data sheet, the various figures and
text refer to DQs as DQ.The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
Additionally, the x16 is divided in to two bytes
the lower byte and upper byte. For the lower byte
(DQ0 through DQ7) DM refers to LDM and DQS
refers to LDQS; and for the upper byte (DQ8 through
DQ15) DM refers to UDM and DQS refers to UDQS.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 Rev. C; Pub. 4/01
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.



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TABLE OF CONTENTS
Functional Block Diagram 32 Meg x 4 ...............
Functional Block Diagram 16 Meg x 8 ...............
Functional Block Diagram 8 Meg x 16 .............
Pin Descriptions ......................................................
4
5
6
7
Functional Description .........................................
Initialization ......................................................
Register Definition .............................................
Mode Register ...............................................
Burst Length ............................................
www.DataSheet4U.com Burst Type ................................................
Read Latency ...........................................
Operating Mode ......................................
Extended Mode Register ...............................
DLL Enable/Disable .................................
9
9
9
9
9
10
11
11
12
12
Commands ............................................................
Truth Table 1 (Commands) ........................................
Truth Table 1A (DM Operation) ..................................
Deselect ..............................................................
No Operation (NOP) ........................................
Load Mode Register ..........................................
Active ................................................................
Read ................................................................
Write ................................................................
Precharge ...........................................................
Auto Precharge ..................................................
Burst Terminate .................................................
Auto Refresh ......................................................
Self Refresh ........................................................
13
13
13
14
14
14
14
14
14
14
14
14
15
15
Operation ..............................................................
Bank/Row Activation .......................................
Reads ................................................................
Read Burst ....................................................
Consecutive Read Bursts ..............................
Nonconsecutive Read Bursts .......................
Random Read Accesses ................................
Terminating a Read Burst ............................
Read to Write ...............................................
Read to Precharge .........................................
Writes ................................................................
Write Burst ...................................................
Consecutive Write to Write .........................
Nonconsecutive Write to Write ..................
16
16
17
18
19
20
21
23
24
25
26
27
28
29
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
Random Writes ............................................
Write to Read Uninterrupting ..................
Write to Read Interrupting .......................
Write to Read Odd, Interrupting .............
Write to Precharge Uninterrupting ..........
Write to Precharge Interrupting ...............
Write to Precharge Odd, Interrupting ......
Precharge ...........................................................
Power-Down .....................................................
Truth Table 2 (CKE) .................................................
Truth Table 3 (Current State, Same Bank) .....................
Truth Table 4 (Current State, Different Bank) .................
30
31
32
33
34
35
36
37
37
38
39
41
Operating Conditions
Absolute Maximum Ratings ....................................
DC Electrical and Operating Conditions ...................
AC Input Operating Conditions ...........................
Clock Input Operating Conditions .......................
Input Voltage .........................................................
Capacitance x4, x8 ..............................................
IDD Specifications and Conditions x4, x8 ...........
Capacitance x16 ..................................................
IDD Specifications and Conditions x16 ...............
AC Electrical Characteristics (Timing Table) ..........
Slew Rate Derating Tables ......................................
Derating Data Valid Window ...............................
43
43
43
44
45
46
46
47
47
48
49
51
Voltage and Timing Waveforms
Normal Output Drive Curves ...........................
Reduced Output Drive Curves (x16 only) ........
Output Timing tDQSQ and tQH x4, x8 .....
Output Timing tDQSQ and tQH x16 .........
Output Timing tAC and tDQSCK .................
Input Timing .....................................................
Initialize and Load Mode Registers ..................
Power-Down Mode ..........................................
Auto Refresh Mode ...........................................
Self Refresh Mode .............................................
Reads
Bank Read Without Auto Precharge ........
Bank Read With Auto Precharge ..............
Writes
Bank Write Without Auto Precharge .......
Bank Write With Auto Precharge .............
Write DM Operation ................................
66-pin TSOP dimensions ........................................
54
55
56
57
58
58
59
60
61
62
63
64
65
66
67
68
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 Rev. C; Pub. 4/01
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.



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PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 4
CKE
CK#
CK
www.DataSheet4CUS#.com
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
12
REFRESH 12
COUNTER
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 8)
SENSE AMPLIFIERS
8192
4
8 READ
LATCH 4
MUX
CK
DATA
DLL
4
DQS
GENERATOR
DRVRS
1
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
10
11 COUNTER/
LATCH
1
I/O GATING
DM MASK LOGIC
1024
(x8)
COLUMN
DECODER
8
COL0
INPUT
REGISTERS
DQS
MASK
1
WRITE
1
8
FIFO
2
&
DRIVERS
4
8
ck ck
4
out in DATA
1
1
1
RCVRS
4
4
4
CK
COL0
1
DQ0 -
DQ3, DM
DQS
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 Rev. C; Pub. 4/01
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.



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