25DF081 Datasheet PDF - ATMEL Corporation

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25DF081
ATMEL Corporation

Part Number 25DF081
Description AT25DF081
Page 30 Pages


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Features
Single 1.65V - 1.95V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
66 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– Sixteen 64-Kbyte Physical Sectors
Hardware Controlled Locking of Protected Sectors
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 8 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil wide)
– 8-contact Ultra Thin DFN (5 mm x 6 mm x 0.6 mm)
– 11-ball dBGA (WLCSP)
8-megabit
1.65-volt
Minimum
SPI Serial Flash
Memory
AT25DF081
1. Description
The AT25DF081 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DF081 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
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The AT25DF081 also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DF081 incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, and
erase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is required
for programming and erasing.
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2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI
SO
WP
HOLD
VCC
GND
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
“Protection Commands and Features” on page 12 for more details on protection features and the
WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI
pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on
page 27 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the system
ground.
Asserted
State
Low
Low
Low
Type
Input
Input
Input
Output
Input
Input
Power
Power
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Figure 2-1. 8-SOIC Top View
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
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Figure 2-2. 8-UDFN Top View
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
Figure 2-3. 11-dBGA (Top View
Through Back of Die)
1234
A
NC
B
VCC CS
C
HOLD SO
D
SCK WP
E
SI GND
F
NC NC
3. Block Diagram
CONTROL AND
CS PROTECTION LOGIC
SCK
SI
SO
INTERFACE
CONTROL
AND
LOGIC
Y-DECODER
WP
HOLD
X-DECODER
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
Y-GATING
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
4 AT25DF081
3674E–DFLASH–8/08



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