20N50E Datasheet PDF - ON Semiconductor

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20N50E
ON Semiconductor

Part Number 20N50E
Description MTW20N50E
Page 8 Pages


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MTW20N50E
Preferred Device
Power MOSFET
20 Amps, 500 Volts
N–Channel TO–247
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage–blocking capability without degrading
performance over time. In addition, this advanced Power MOSFET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage
– Continuous
– Non–Repetitive (tp 10 ms)
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
500
500
± 20
± 40
20
14.1
60
250
2.0
Operating and Storage Temperature Range TJ, Tstg –55 to
150
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL = 20 Apk, L = 10 mH, RG = 25 )
Thermal Resistance – Junction to Case
Thermal Resistance – Junction to Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10 seconds
EAS
RθJC
RθJA
TL
2000
0.50
40
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
°C/W
°C
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20 AMPERES
500 VOLTS
RDS(on) = 240 m
N–Channel
D
G
1
23
S
4
TO–247AE
CASE 340K
Style 1
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTW20N50E
LLYWW
1
Gate
3
Source
2
Drain
LL = Location Code
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTW20N50E
TO–247
30 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 5
1
Publication Order Number:
MTW20N50E/D



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MTW20N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
500
583
– Vdc
– mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
µAdc
– – 10
– – 100
IGSS – – 100 nAdc
VGS(th)
2.0 3.0 4.0 Vdc
– 7.0 – mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 20 Adc)
(ID = 10 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 250 Vdc, ID = 20 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 20 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (Note 1.)
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
– 0.20 0.24 Ohm
Vdc
– 5.75 6.0
– – 6.0
11 16.2
– mhos
3880 6950
pF
– 452 920
– 96 140
– 29 55 ns
– 90 165
– 97 190
– 84 170
– 100 132 nC
– 20 –
– 44 –
– 36 –
Vdc
0.916
1.1
– 0.81 –
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored
Charge
(IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
trr
ta
tb
QRR
– 431 –
– 272 –
– 159 –
– 6.67 –
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
LD – 5.0 – nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
1. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
2. Switching characteristics are independent of operating junction temperature.
LS
– 13 – nH
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MTW20N50E
TYPICAL ELECTRICAL CHARACTERISTICS
40
TJ = 25°C
32
VGS = 10 V
9V
8V
24 7 V
16
6V
8
5V
0
0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
40
VDS 10 V
32
24
16 100°C
8 25°C
TJ = -55°C
0
2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.6
VGS = 10 V
0.5
0.4
0.3
TJ = 100°C
25°C
0.2
-55°C
0.1
0
04
8 12 16 20 24 28 32 36 40
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
0.34
TJ = 25°C
0.32
0.30
0.28 VGS = 10 V
0.26 15 V
0.24
0 4 8 12 16 20 24 28 32 36 40
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.4
VGS = 10 V
2.0 ID = 10 A
1.6
10000
VGS = 0 V
1000
TJ = 125°C
100°C
1.2 100
0.8
10
0.4 25°C
0
-Ă50 -Ă25
0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
1
0 50 100 150 200 250 300 350 400 450 500
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
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MTW20N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
9000
8000 VDS = 0 V
7000 Ciss
VGS = 0 V
TJ = 25°C
6000
5000
4000 Crss
Ciss
3000
2000
1000
0
10
Crss
505
VGS VDS
Coss
10 15
20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
10000
VGS = 0 V
1000
TJ = 25°C
Ciss
100
10
10
Coss
Crss
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
1000
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