16C550 Datasheet PDF - ETC

www.Datasheet-PDF.com

16C550
ETC

Part Number 16C550
Description TL16C550
Page 30 Pages


16C550 datasheet pdf
Download PDF
16C550 pdf
View PDF for Mobile

No Preview Available !

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
www.DataSheet4U.com Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
D False-Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 × clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1



No Preview Available !

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
N PACKAGE
(TOP VIEW)
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
www.DataSheet4U.com
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 RI
38 DCD
37 DSR
36 CTS
35 MR
34 OUT1
33 DTR
32 RTS
31 OUT2
30 INTRPT
29 RXRDY
28 A0
27 A1
26 A2
25 ADS
24 TXRDY
23 DDIS
22 RD2
21 RD1
FN PACKAGE
(TOP VIEW)
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
AS
NC – No internal connection
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



No Preview Available !

block diagram
Internal
Data Bus
8 –1
D7 – D0
Line
Control
Register
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
S
e
l
e
c
t
Receiver
Buffer
Register
Receiver
FIFO
Receiver
Buffer
Register
10
SIN
www.DataSheet4U.com
28
A0
27
A1
26
A2
12
CS0
13
CS1
14
CS2
25
ADS
35
MR
21
RD1
22
RD2
18
WR1
WR2 19
DDIS 23
TXRDY 24
XIN 16
XOUT 17
RXRDY 29
Select
and
Control
Logic
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
40
VCC
20
VSS
Power
Supply
Interrupt
Enable
Register
Interrupt
I/O
Register
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the N package.
Baud
Generator
Transmitter
FIFO
S
e
l
e
c
t
Interrupt
Control
Logic
Receiver
Timing and
Control
9
RCLK
15
BAUDOUT
Line
Control
Register
Line
Control
Register
Modem
Control
Logic
11
SOUT
32
RTS
36
CTS
33 DTR
37
DSR
38
DCD
39
RI
34
OUT1
31
OUT2
30
INTRPT
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



No Preview Available !

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Terminal Functions
TERMINAL
NAME
NO.† I/O
DESCRIPTION
A0 28 [31] I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from
A1
27 [30]
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.
A2 26 [29]
ADS
25 [28] I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.
BAUDOUT 15 [17] O Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.
www.DataSheCeSt40U.com 12 [14] I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
CS1
13 [15]
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.
CS2 14 [16]
CTS
36 [40] I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.
D0 – D7
1 – 8 I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
[2 – 9]
ACE and the CPU.
DCD
38 [42] I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes
state, an interrupt is generated.
DDIS
23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an external transceiver.
DSR
37 [41] I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.
DTR
33 [37] O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level.
DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing
bit 0 (DTR) of the modem control register.
INTRPT
30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.
MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
to Table 2.
OUT1
OUT2
34 [38] O Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
31 [35]
their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.
RCLK
9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RD1
21 [24] I Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
RD2
22 [25]
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).
Terminal numbers shown in brackets are for the FN package.
4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



16C550 datasheet pdf
Download PDF
16C550 pdf
View PDF for Mobile


Related : Start with 16C55 Part Numbers by
16C550 TL16C550 16C550
ETC
16C550 pdf
16C552 Dual FIFO UART and Parallel Port 16C552
IMP Inc
16C552 pdf
16C554 PIC16C554 16C554
Microchip Technology
16C554 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact